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test-r3hi61/ rpocr3hi61

0 0

Updated 2026-11-07 16:56:18 +00:00

poc_dacf2983/ poc-dacf2983

0 0

Updated 2026-10-30 12:51:07 +00:00

poc_3fff4799/ poc-3fff4799

0 0

Updated 2026-10-26 15:57:25 +00:00

poc_89782693/ poc-89782693

0 0

Updated 2026-10-26 15:52:35 +00:00

test-5lc4ys/ rpoc5lc4ys

0 0

Updated 2026-10-21 17:03:46 +00:00

test-wwfea7/ rpocwwfea7

0 0

Updated 2026-10-20 07:04:51 +00:00

un6otk1/ ruz1a38

Shell 0 0

Updated 2026-08-07 09:10:19 +00:00

u3lvfy8/ rrtxbmv

Shell 0 0

Updated 2026-08-07 09:09:13 +00:00

utenhjs/ ruk965m

Shell 0 0

Updated 2026-08-07 09:07:13 +00:00

uincqs9/ r224jm9

Shell 0 0

Updated 2026-08-07 09:06:55 +00:00

uiu4e3e/ r7ovngm

Shell 0 0

Updated 2026-08-07 09:03:02 +00:00

u30lvgm/ rf4n6a0

Shell 0 0

Updated 2026-08-07 08:34:10 +00:00

sBubshait/ FPGABench

CSS 0 0

FPGABench evaluates whether language models can generate FPGA-ready Verilog: not just code that simulates correctly, but designs that synthesize and meet real timing, resource, and power constraints.

Updated 2026-06-13 19:28:36 +00:00

sBubshait/ ResBench

Python 0 0

ResBench adapted from https://github.com/jultrishyyy/ResBench

Updated 2025-12-17 18:57:17 +00:00