sBubshait ff0bb64e6e chore: allow all hosts in vite config

2026-06-13 17:23:45 +01:00

dist

feat: fix bug

2026-06-13 17:13:50 +01:00

node_modules

first commit

2026-06-13 15:59:39 +01:00

app.js

first commit

2026-06-13 15:59:39 +01:00

index.html

feat: fix bug

2026-06-13 17:13:50 +01:00

package-lock.json

first commit

2026-06-13 15:59:39 +01:00

package.json

feat: update --host

2026-06-13 17:21:23 +01:00

style.css

first commit

2026-06-13 15:59:39 +01:00

vite.config.js

chore: allow all hosts in vite config

2026-06-13 17:23:45 +01:00

Description

FPGABench evaluates whether language models can generate FPGA-ready Verilog: not just code that simulates correctly, but designs that synthesize and meet real timing, resource, and power constraints.

6.1 MiB

Languages

CSS 37.7%

JavaScript 37.5%

HTML 24.8%